1. Field of the Invention
This invention relates generally to the testing of digital signal processing units and, more particularly, to the signals that are transmitted from a target processor to a host processing to permit analysis of the target processor operation. Certain events in the target processor must be communicated to the host processing unit along with contextual information. In this manner, the test and debug data can be analyzed and problems in the operation of the target processor identified.
2. Description of the Related Art
As microprocessors and digital signal processors have become increasingly complex, advanced techniques have been developed to test these devices. Dedicated apparatus is available to implement the advanced techniques. Referring to FIG. 1A, a general configuration for the test and debug of a target processor 12 is shown. The test and debug procedures operate under control of a host processing unit 10. The host processing unit 10 applies control signals to the emulation unit 11 and receives (test) data signals from the emulation unit 11 by cable connector 14. The emulation unit 11 applies control signals to and receives (test) signals from the target processing unit 12 by connector cable 15. The emulation unit 11 can be thought of as an interface unit between the host processing unit 10 and the target processor 12. The emulation unit 11 processes the control signals from the host processor unit 10 and applies these signals to the target processor 12 in such a manner that the target processor will respond with the appropriate test signals. The test signals from the target processor 12 can be a variety types. Two of the most popular test signal types are the JTAG (Joint Test Action Group) signals and trace signals. The JTAG protocol provides a standardized test procedure in wide use in which the status of selected components is determined in response to control signals from the host processing unit. Trace signals are signals from a multiplicity of selected locations in the target processor 12 during defined period of operation. While the width of the bus 15 interfacing to the host processing unit 10 generally has a standardized dimension, the bus between the emulation unit 11 and the target processor 12 can be increased to accommodate an increasing amount of data needed to verify the operation of the target processing unit 12. Part of the interface function between the host processing unit 10 and the target processor 12 is to store the test signals until the signals can be transmitted to the host processing unit 10.
In testing the target processors, certain events must be identified by the host processing unit. To understand the origin of the program flush sync point, portions of the target processor must be considered in more detail. Referring to FIG. 1B, the target processor pipeline 127 executes program instructions. After the instruction has been processed by the processor pipeline 127, an access of the memory unit 128 results in a delay. To accommodate this delay, the instruction, is placed in a pipeline flattener 129. The pipeline flattener 129 is similar to a first in-first out storage unit. However, the instruction remains in the pipeline flattener 129 until the results of the memory unit access are stored in the location along with the instruction. When the pipeline flattener 129 becomes full, a new instruction results in the transfer from the pipeline flattener 129 to the appropriate location in the target processor.
Referring to FIG. 1C, the secondary (interrupt) code execution has been halted or completed (upper graph) and another primary code begins execution (middle graph). The lower graph illustrates that the results of the program execution are being withdrawn from the pipeline flattener. At the breakpoint in the secondary code execution, both the unprotected processor pipeline and the pipeline flattener halt operation. Although instruction results are no longer being transferred to or from the pipeline flattener, the results of the memory accesses are still being added to the instruction locations in the pipeline flattener. After some period of time, the primary (typically program) code execution begins. As a result of the primary code execution, the pipeline flattener transfers instruction results from the secondary code execution before transferring the results of primary code execution. This first portion of the output of the pipeline flattener following the beginning of the primary code execution is designated a “flush” in FIG. 1C. It is important to communicate to the host processing unit where the flush portion from the pipeline flattener ends because this point is actual end point of the secondary code execution prior to initiation of the primary code execution.
A need has been felt for apparatus and an associated method having the feature that a point at the end of the secondary code execution flush region is identified in a target processor and that the end point of the flush region is communicated to the testing apparatus. It is another feature of the apparatus and associated method to transfer information concerning a flush region to the testing processing unit using the trace stream. It is a still further feature of the apparatus and associated method to communicate to the testing apparatus when the flush region is identified during the program execution.